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| publication number s73ws256n_00 revision a amendment 3 issue date december 16, 2005 s73ws256n based mcps stacked multi-chip product (mcp) 512/256 megabit (32m/16m x 16-bit) cmos 1.8 volt-only, simultaneous read/write, burst mode flash memory with 256/128 megabit (4m/2m x 16-b it x 4 banks) mobile sdram on shared data bus data sheet advance information ! "# $ % % & ii s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information notice on data sheet designations ''( ) * + ) , * ) ''( * ) - * ''( ) . " ''( % ) * ''( )- ) & - + + ( / ) - * ) . " + % + + + * & ) ) * ! ) ) ) %(( ( 0 / # - 1 $ ( * ''( ) . " ''( * + / 2) & 3 4%! 5 publication number s73ws256n_00 revision a amendment 3 issue date december 16, 2005 distinctive characteristics ) 676891 ! " ! .:; ! + . 9<42, ==42, :;42, 4 %> 4 + .6;<42, - . ?8;/6@; $ ?a@9b(c:9b() general description 7d0 - 4 *( 4( - . $ ) $ 4 %> 4 e ! 4 %> 4.8=* )! . s73ws256n based mcps stacked multi-chip product (mcp) 512/256 megabit (32m/16m x 16 -bit) cmos 1.8 volt-only, simultaneous read/write, burst mode flash memory with 256/ 128 megabit (4m/2m x 16-bit x 4 banks) mobile sdram on shared data bus data sheet advance information flash memory density 256mb 512mb # 6@:4 7d0@9=#%; 7d0@9=#% @9=4 7d0@9=# 2 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information 1 product selector guide device-model# flash density (code) flash density (data) flash initial/burst speed (ns/mhz) sdram density sdram burst speed (mhz) supplier dy b package 7d0@9=#%;f 0 7 @9=4 ? :; e9<42, 6@: 6;<42, 6 8/6@/6@ 6d7* 7d0@9=#%;f 0 f @ 7d0@9=#%f 07 @9=4 @9=4 :; e9<42, 6@: 6;<42, 6 8/6@/6< 6d7* 7d0@9=#%f 0f @ 7d0@9=#f 07 @9= 6 7d0@9=#f 0f @ 7d0@9=#%;f!0 7 @9=4 ? :; e9<42, 6@: 6;<42, 6 8/6@/6@ 6d7* 7d0@9=#%;f!0 f @ 7d0@9=#%f!07 @9=4 @9=4 :; e9<42, 6@: 6;<42, 6 8/6@/6< 6d7* 7d0@9=#%f!0f @ 7d0@9=#f!07 @9= 6 7d0@9=#f!0f @ december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 3 advance information table of contents s73ws256n based mcps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i 1 product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 connection diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 2 x 256mb flash with 256mb sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 2 x 256mb flash with 128mb sdram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 256mbflash with 128mb sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 lookahead diagram on shared bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 logic symbol for mcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 tld137137-ball fine-pitch ball grid arra y (fbga) 9 x 12.0 mm package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 ftf137137-ball fine-pitch ball grid array (fbga) 9 x 12.0 x 1.4 mm package . . . . . . . . . . . . . . . . . . . . . . . . . .21 8 input/output descriptions & logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11 product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12.3 page read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12.4 synchronous (burst) read mode & config uration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12.4.1 continuous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12.4.2 8-, 16-, 32-word linear bu rst read with wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 12.4.3 8-, 16-, 32-word linear bu rst without wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 12.4.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 12.5 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.6 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.6.1 single word programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.6.2 write buffer programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.6.3 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.6.4 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.6.5 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.6.6 program suspend/prog ram resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.6.7 accelerated program/chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.6.8 unlock bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.6.9 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.7 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.8 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.9 handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.10 hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.11 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2 persistent protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.3 dynamic protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.4 persistent protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.6 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.7 hardware data protection me thods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.7.1 wp# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information 13.7.2 acc method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.7.3 low v cc write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.7.4 write pulse glitch protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.7.5 power-up write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14 power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 14.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.2 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.3 hardware reset# input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 15.1 factory secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 15.2 customer secured silicon sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 15.3 secured silicon sector entry/exit comma nd sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 16.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 16.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.6 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.7 dc characteristics (cmos compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.8.1 clk characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.8.2 synchronous/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 16.8.3 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 16.8.4 ac characteristicsasynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 16.8.5 hardware reset (res et#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 16.8.6 erase/program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 16.8.7 erase and programming performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 16.8.8 bga ball capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 17 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 17.1 common flash memory interfac e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 18 revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 mobile sdram type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 19 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 20 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 21 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 22 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 23 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 24 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 25 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 26 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 27 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 28 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 29 write burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 30 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 31 temperature compensated self refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 32 partial array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 33 driver strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 34 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 35 command inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 36 no operation (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 37 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 38 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 39 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 5 advance information 40 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 41 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 42 auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 43 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 44 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 45 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 46 deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 47 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 47.1 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 47.2 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 47.3 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 47.4 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 47.5 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 47.6 deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 47.7 clock suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 47.8 burst read/single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 47.9 concurrent auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 47.9.1 read with auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 47.10 write with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 48 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 49 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 49.1 revision a0 (april 1, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 49.2 revision a1 (april 25, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 49.3 revision a2 (april 25, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 49.4 revision a3 (april 25, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 mobile sdram type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 50 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 51 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 52 capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 53 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 54 ac operating test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 55 operating ac parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 56 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 57 simplified truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 58 mode register field table to program modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 59 normal mrs mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 60 emrs for pasr (partial a rray self ref) & ds (driver strength) . . . . . . . . . . . . . . . . . . . . 169 61 partial array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 62 internal temperature compensated self refresh (tcsr) . . . . . . . . . . . . . . . . . . . . . . . . . 170 63 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 64 burst sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 64.1 burst length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 64.2 burst length = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 65 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 65.1 addresses of 64mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 65.1.1 bank addresses (ba0 ~ ba1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 65.1.2 address inputs (a0 ~ a11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 65.2 addresses of 128mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 65.2.1 bank addresse s (ba0 ~ ba1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 65.2.2 address inputs (a0 ~ a11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 65.3 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 65.4 clock enable (cke). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 65.5 nop and device deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 65.6 dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 65.7 mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information 65.8 extended mode register set (emrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 65.9 bank activate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 65.10 burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 65.11 burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 65.12 all banks precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 65.13 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 65.14 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 65.15 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 65.16 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 65.17 basic feature and function descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 65.17.1 auto refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 65.17.2 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 66 about burst type control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 67 about burst length control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 68 function truth table (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 69 function truth table (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 70 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 71 sdram type 2 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 mobile sdram type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 72 address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 73 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 74 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 75 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 76 capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 77 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 78 ac operating test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 08 79 operating ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 80 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 81 simplified truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 82 mode register field table to program modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 82.1 normal mrs mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 82.2 emrs for pasr (partial array self refresh) and ds (driver strength) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 83 partial array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 83.1 internal temperature compensated self refresh (tcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 84 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 85 burst sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 85.1 burst length = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 85.2 burst length = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 86 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 86.1 addresses of 256mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 86.1.1. bank addresses (ba0-ba1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 86.1.2 address inputs (a0-a12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 86.2 addresses of 512mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 86.2.1. bank addresses (ba0-ba1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 86.2.2 address inputs (a0-a12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 86.3 clock (clk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 86.4 clock enable (cke). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 86.5 nop and device deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 86.6 dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 86.7 mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 86.8 extended mode register set (emrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 86.9 bank activate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 86.10 burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 86.11 burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 86.12 all banks precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 7 advance information 86.13 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 86.14 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 86.15 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 86.16 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 87 basic feature and function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 87.1 clock suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 87.2 dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 87.3 cas# interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 87.4 cas# interrupt 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 87.5 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 87.6 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 88 burst type control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 89 burst length control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 90 function truth table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 91 function truth table 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 92 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 93 sdram type 2 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 94 mcp revision summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 8 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information list of tables :6 e$ % @d 666 @80@9=# g4 4 @= 66@ @806@:# g4 4 @7 6@6 % $ @: 6@@ 0 ) @8 6@d ' @80@9=# d6 6@< ' @806@:# d6 6@9 ef ( ' @80@9=#h:;42, d 6 6@= ef ( ' @80@9=#h==42, d 6 6@7 ef ( ' @80@9=#h9<42, d 6 6@: ef ( ' @806@:# d6 6@8 f i dd 6@6; ( > d< 6@66 d9 6@6@ d= 6@6d / d= 6@6< 0 d8 6@69 0 f <6 6@6= <= 6@@; <7 6@@6 > <7 6@@@ j -f <: 6@@d j -f <8 6@@< j -f> <8 6@@9 %3= %3@ 9d 6@@= 0 $ 99 6@@7 > 97 6d6 ' -> =; 6d@ == 696 =8 69@ 76 69d 76 69< / 76 6=6 7d 6=@ 0 > + 77 676 4 ( 87 67@ ( 8: 67d (! 3 88 67< 88 679 % i % 6;; 67= 1 * / 3 6;6 @96 f % 66; @76 ( ' 66@ d<6 6*( %34$ 669 <76 @*(k 6d9 <7@ d*( f - ( f - 6d= <7d <*( f - ( f - 6d7 <:6 %( ( $ ( 6d8 <:@ ( ( $ ( 6<; <:d ( > ($ ( 6 <; <:< (! ( 6<6 <:9 %% ( 6<@ <:= %%7 * > ( $ 6 december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 9 advance information list of figures ! 86 @80*#f -% @< ! 6@6 e % d; ! 6@@ > d@ ! 6@d 0 d: ! 6@< 0 f $ <@ ! 6@9 $ << ! 6@= 0 $ !) 96 ! 6d6 ej 98 ! 6d@ f e =@ ! 6dd ' -> =9 ! 6=6 4/ # $ 0 7@ ! 6=@ 4/ $ 0 7@ ! 6=d 7d ! 6=< 0 4 ' 7< ! 6=9 1 (( ) * % 7< ! 6== ('k( , 7= ! 6=7 ('k f 4 > 7: ! 6=: :*)' f )0 78 ! 6=8 :*)' f ) 0 78 ! 6=6; ' f )> %l $ ( f % :; ! 6=66 4 > :6 ! 6=6@ ! *0 *4 $ :6 ! 6=6d > :@ ! 6=6< (e $ :< ! 6=69 $ j 1%m :9 ! 6=6= $ j ('k > 1%m := ! 6=67 j -f :7 ! 6=6: %m % :7 ! 6=68 f % :: ! 6=@; % e f :: ! 6=@6 ( %3@ % :8 ! 6=@@ ( %3@ m6 :8 ! 6=@d ( %3@ m@ :8 ! 6=@< ( %3@ md :8 ! 6=@9 %3@ %3= 8; ! 6=@= ' )f ( ) ! + n==42, 8; ! 6=@7 ' )f ( e f - 86 ! 6=@: / 0 8@ ! 6=@8 f -**f -> e0 ( 8d ! @;6 f -% 6;= ! @96 4 > % 666 ! @76 ( ' 66@ ! dd6 / 4 > 66< ! <76 >) f -> 668 ! <76 > ( 6@6 ! <76 0 ( 6@= ! <:6 , '4 > 6<< ! 9<6 %($ '( 6=9 ! 9<@ ($ '( 6== ! =96 ( - 679 ! =9@ %34$ 67= ! =9d ( m 6 677 ! =9< ( m @.> 0 g%34 67: ! =99 0 g %34 678 ! =9= 678 ! =97 6:; ! =9: f 6:; ! =98 4> 6:6 10 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information ! =96; ( - / ) %) / 6:6 ! =966 > 6:6 ! =96@ > 6:@ ! 7;6 ) j + 4 %> 4 6:= ! 7;@ f> *0 *> ( h( ' od f ' o6 6:7 ! 7;d > g0 ( f -hf ' o< >%' o@('k 6:: ! 7;< > g0 ( f -hf ' o< >%' o@('k 6:8 ! 7;9 > ( % f -hf ' o< 68; ! 7;= 0 ( % f -hf ' o< >%' o@('k 686 ! 7;7 > g0 ( % f -hf ' o< 68@ ! 7;: > g0 ( ) 6hf ' o< 68d ! 7;8 > g0 ( ) @hf ' o< 68< ! 7;6; ( - g%34$ ( h( ' o@ f ' o< 689 ! 7;66 > ( g> f ( h! f 68= ! 7;6@ 0 ( g0 f ( h! f >%' o@('k 687 ! 7;6d f > 0 ( hf ' o@ 68: ! 7;6< e ) %) 4 h( ' o@ f ' o< 688 ! 7;69 > g/( @;; ! 7;6= 4 > ( > ( @;6 ! 7;67 / 4 > ( @;@ ! 7:6 %($ '( @;: ! 7:@ ($ '( @;8 ! :d6 > @6d ! :76 ( - % 0 @68 ! :7@ ( - % > f'o< @68 ! :76 0 4-f'o< @68 ! :7@ > 4-f'o< @@; ! :7d %34)(' - ! > @@; ! :7< > > f'o< @@; ! :79 0 0 f'o @ @@; ! :7= 0 > f'o@ @@6 ! :77 > 0 %34 @@@ ! :7: 0 %34 @@d ! :78 @@d ! :76; @@< ! :766 f @@9 ! :76@ 4 > @@9 ! :76d ( - / ) %) / @@= ! :76< > @@= ! :769 > @@= ! 8@6 ) j + @d6 ! 8@@ f> *0 *> ( h( ' od f ' o6 @d@ ! 8@d > g0 ( f -hf ' o< >%' o@('k @dd ! 8@< > g0 ( f -hf ' o< >%' o@('k @d< ! 8@9 > ( % f -hf ' o< @d9 ! 8@= 0 ( % f -hf ' o< >%' o@('k @d= ! 8@7 > g0 ( % f -hf ' o< @d7 ! 8@: > g0 ( ) hf ' o< @d: ! 8@8 > g0 ( ) @hf ' o< @d8 ! 8@6; ( - g%34$ ( h( ' o@ f ' o< @<; ! 8@66 > ( g> f ( h! f @<6 ! 8@6@ 0 ( g0 f ( h! f >%'o@('k @<@ ! 8@6d f > 0 ( hf ' o@ @ ' o< @<< ! 8@69 > g/( @<9 ! 8@6= / 4 > ( @<7 december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 11 advance information 2 mcp block diagram !"#$ %% # #& !'( !'& ) # * +), (-.! +), (-. / v id v cc rdy sdram flash 1 dq15 to dq0 a23 - a0 (note 1) ce#f1 acc d-ba1 d-ras# d-v cc v cc v ccq v cc f max +1* clk clk wp#f1 oe# we# reset# avd# ce# acc wp# oe# we# reset# avd# rdy v ss v ssq dq15 to dq0 16 dq15 to dq0 16 d-ce# ce# we# ba0 cke d-max + 1* ce#f2 clk flash 2 (note 2) d-v ccq a12 - a0 d-clk d-we# d-ba0 ba1 d-cke ras# cas# d-dm0 dm0 d-dm1 dm1 d-cas# d-v ssq * amax = a23 d-amax = a12 12 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information 3 connection diagrams 3.1 2 x 256mb flash with 256mb sdram 0 !"#$1 1 ' ! 1 0 !"#$1 1 ' ! 1 #$ ! %& ' + ! 4 !fi - ! !fi - / * - e - / 69; ( * sdram only legend reserved for future use a1 a10 b9 b2 a2 a9 b1 b10 c4 c7 c8 c9 c3 c2 c6 c5 d4 d7 d8 d3 d2 d6 d5 e4 e7 e8 e9 e3 e2 e6 e5 f4 f7 f8 f9 f3 f2 f6 f5 g4 g7 g8 g9 g3 g2 g6 h4 h7 h8 h9 h3 h2 j4 j7 j8 j9 j3 j2 j6 j5 k4 k7 k8 k9 k3 k2 k6 k5 l4 l7 l8 l9 l3 l2 l6 l5 m4 m7 m8 m9 m3 m2 m6 m5 n9 n2 n1 n10 p9 p2 p1 p10 flash/sdram shared d-cke d-clk d-vss d-ce# d-ras# d-we# rfu d-cas# avd# vss clk rfu rfu rfu rfu rfu wp# a7 d-dm0 acc we# a8 a11 f2-ce# a3 a6 d-dm1 f-rst# rfu a19 a12 a15 a2 a5 a18 rdy a20 a9 a13 a21 a1 a4 a17 a23 a10 a14 a22 a0 vss dq1 dq6 rfu a16 f1-ce# oe# dq9 dq3 dq4 dq13 dq15 rfu rfu dq0 dq10 f-vcc d-vcc dq12 dq7 vss d-vcc dq8 dq2 dq11 rfu dq5 dq14 rfu rfu rfu vss f-vcc rfu rfu rfu rfu rfu d-ba0 d-ba1 rfu rfu d-vss rfu rfu data flash only flash/data shared d9 code flash only a4 a7 a8 a3 a6 a5 b4 b7 b8 b3 b6 b5 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu n4 n7 n8 n3 n6 n5 p4 p7 p8 p3 p6 p5 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu c1 d1 e1 f1 g1 h1 j1 k1 l1 m1 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu c10 d10 e10 f10 g10 h10 j10 k10 l10 m10 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu do not use ()*+ +"% & 1 ) f! %) december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 13 advance information 3.2 2 x 256mb flash with 128mb sdram 0 !"#$1 1 ' ! 1 0 !"#$1 1 ' ! 1 #$ ! %& ' + ! 4 !fi - ! !fi - / * - e - / 69; ( * sdram only legend reserved for future use a1 a10 b9 b2 a2 a9 b1 b10 c4 c7 c8 c9 c3 c2 c6 c5 d4 d7 d8 d3 d2 d6 d5 e4 e7 e8 e9 e3 e2 e6 e5 f4 f7 f8 f9 f3 f2 f6 f5 g4 g7 g8 g9 g3 g2 g6 h4 h7 h8 h9 h3 h2 j4 j7 j8 j9 j3 j2 j6 j5 k4 k7 k8 k9 k3 k2 k6 k5 l4 l7 l8 l9 l3 l2 l6 l5 m4 m7 m8 m9 m3 m2 m6 m5 n9 n2 n1 n10 p9 p2 p1 p10 flash/sdram shared d-cke d-clk d-vss d-ce# d-ras# d-we# rfu d-cas# avd# vss clk rfu rfu rfu rfu rfu wp# a7 d-dm0 acc we# a8 a11 f2-ce# a3 a6 d-dm1 f-rst# rfu a19 a12 a15 a2 a5 a18 rdy a20 a9 a13 a21 a1 a4 a17 a23 a10 a14 a22 a0 vss dq1 dq6 rfu a16 f1-ce# oe# dq9 dq3 dq4 dq13 dq15 rfu rfu dq0 dq10 f-vcc d-vcc dq12 dq7 vss d-vcc dq8 dq2 dq11 rfu dq5 dq14 rfu rfu rfu vss f-vcc rfu rfu rfu rfu rfu d-ba0 d-ba1 rfu rfu d-vss rfu rfu data flash only flash/data shared d9 code flash only n4 n7 n8 n3 n6 n5 p4 p7 p8 p3 p6 p5 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu c1 d1 e1 f1 g1 h1 j1 k1 l1 m1 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu c10 d10 e10 f10 g10 h10 j10 k10 l10 m10 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu a4 a7 a8 a3 a6 a5 b4 b7 b8 b3 b6 b5 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu do not use ()*+ +"% & 1 ) f! %) 14 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information 3.3 256mbflash with 128mb sdram 0 !"#$1 1 ' ! 1 0 !"#$1 1 ' ! 1 #$ ! %& ' + ! 4 !fi - ! !fi - / * - e - / 69; ( * sdram only legend reserved for future use a1 a10 b9 b2 a2 a9 b1 b10 c4 c7 c8 c9 c3 c2 c6 c5 d4 d7 d8 d3 d2 d6 d5 e4 e7 e8 e9 e3 e2 e6 e5 f4 f7 f8 f9 f3 f2 f6 f5 g4 g7 g8 g9 g3 g2 g6 h4 h7 h8 h9 h3 h2 j4 j7 j8 j9 j3 j2 j6 j5 k4 k7 k8 k9 k3 k2 k6 k5 l4 l7 l8 l9 l3 l2 l6 l5 m4 m7 m8 m9 m3 m2 m6 m5 n9 n2 n1 n10 p9 p2 p1 p10 flash/sdram shared d-cke d-clk d-vss d-ce# d-ras# d-we# rfu d-cas# avd# vss clk rfu rfu rfu rfu rfu wp# a7 d-dm0 acc we# a8 a11 rfu a3 a6 d-dm1 f-rst# rfu a19 a12 a15 a2 a5 a18 rdy a20 a9 a13 a21 a1 a4 a17 a23 a10 a14 a22 a0 vss dq1 dq6 rfu a16 f1-ce# oe# dq9 dq3 dq4 dq13 dq15 rfu rfu dq0 dq10 f-vcc d-vcc dq12 dq7 vss d-vcc dq8 dq2 dq11 rfu dq5 dq14 rfu rfu rfu vss f-vcc rfu rfu rfu rfu rfu d-ba0 d-ba1 rfu rfu d-vss rfu rfu d9 code flash only n4 n7 n8 n3 n6 n5 p4 p7 p8 p3 p6 p5 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu c1 d1 e1 f1 g1 h1 j1 k1 l1 m1 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu c10 d10 e10 f10 g10 h10 j10 k10 l10 m10 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu a4 a7 a8 a3 a6 a5 b4 b7 b8 b3 b6 b5 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu do not use ()*+ +"% & 1 ) f! %) december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 15 advance information 3.4 lookahead diagram on shared bus 2 3 ( 4256 ) 7 !6% j4 j5 j6 j7 j8 j9 h7 h8 h9 g7 g7 g8 g9 f7 f7 f8 f8 f9 f9 e7 e7 e8 e8 e9 e9 d5 k3 d6 d6 d7 d7 f1-ce# j3 oe# r-ce1# dq0 d2 d 2 d3 c2 c3 c3 avd# vss wp# d-a7 a8 we# d-dm0/ r-lb# c4 c5 c 5 c6 c 6 c7 d8 d8 d9 d 9 f3-ce# a11 c8 c9 c 9 f2-oe# r-oe# f-clk# f-vcc f2-ce# clk a15 a12 a19 a21 a13 a9 a22 a14 a10 a16 a24 dq6 g6 f6 f6 r-ce2 a20 a23 h4 g4 f4 f4 f5 f5 e5 f-rst# rdy/wait# a18 a17 dq1 r-cre or r-mrs dq15 dq13 dq4 dq3 dq9 k4 k8 k8 k9 k9 dq7 r-vcc f-vcc dq10 h2 h3 g2 g3 f2 f2 f3 f3 e2 e2 e3 e3 a6 a3 a5 a2 a4 a1 vss a0 l4 l5 l6 l7 l8 l8 l9 l 9 l2 l 2 l3 m2 m3 r-vcc dq8 a27 a26 vss dq12 wp# dq14 dq5 a25 dq11 dq2 m4 m6 m 6 m8 m9 f-vccq r-vccq f4-ce# f-vcc vss dd-clk# f-dqs1 f-dqs0 k6 d4 b2 d-we# a2 d-clk b1 a1 d-cke d-ras# b9 d-dqs3 a9 d-vss b10 b10 d-cas# a10 d-ce# d-dqs2 d-ba1 d-dqs1 d-ba0 d-dqs0 p2 d-vss e4 e6 acc m7 d-dm1/ r-ub# n9 p9 p10 n10 n1 n2 p1 m5 m 5 k2 l2 j2 j 2 k5 k 5 b10 b4 dnu a4 dnu b3 a3 dnu dnu b6 dnu a6 dnu b5 a5 dnu dnu b8 dnu a8 dnu b7 a7 dnu dnu dnu dnu d1 c1 dnu dnu h1 g1 f1 e1 dnu dnu dnu dnu dnu dnu l2 l 2 m1 dnu dnu dnu dnu k1 l1 j1 n4 n5 n6 n7 n8 n3 p3 dnu dnu dnu dnu dnu dnu dnu p4 p6 p8 dnu dnu dnu dnu dnu p7 p5 j10 h10 e10 d10 dnu dnu c10 dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu k7 f10 g10 k10 l10 m10 sdram only legend: rfu (reserved for future use) flash/xram shared mirrorbit data only code flash only flash/data shared psram only xram shared 16 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information 4 input/output descriptions @d* ; o ! 6@* ; o %> 4 %369*%3; o ! %> 4 e (m@ o !(* m@ ('k (m6 o !(* m6 ('kf 4 $m o !$ ('kf 0m o !0 1 (( o ! ) 671*6891 1 (( + o e$ f ) 1 oi >!j o > ! j >%l o ! f 1$'o ('k o !( - ('k 5 ) 1%m) ) + ('k ('k ) 1%m o ! 1 1 'o p ('k 1 2o >m o !) 1 'o 0 m o !) ) 1 'o (( o ! 122 p - 1 ' 1 2 %*('k o %> 4 ( - %*(m o %> 4( %*(k o %> 4( - %*f 6*f ; o %> 4f - %*> m o %> 4>) %*( m o %> 4( %*%46*%*%4; o %> 4% e$ 4- %*0m o %> 40 %*1 o %> 4i %*13 o %> 4 e$ f %*1((3 o %> 4 e$ f ) %*1(( o %> 4 ) december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 17 advance information 5 logic symbol for mcp dq15-dq0 a23-a0 oe# we# reset# clk rdy avd# wp# acc ce#f1 16 d-clk# d-ce# d-cke d-ba1-ba0 d-dm1-dm0 d-cas# d-ras# ce#f2 d-we# d-a12-a0 18 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information 6 ordering information ) . s73ws 256 n de ba w a 7 0 ,&-./ ;o @ o 7& > d o 6d& > 0 /12 %/ 7 o %> 4 6 6;<42,*%lfq 6q ) f o %> 4 @ 6;<42,*%lfq 6q ) ,&/ 0 / o 8/6@; 6@ 6d7 !fi o 8/6@; 6< 6d7 !fi -/ / -2 / &/ 0o0 *@9 (c:9 ( ,&/-./ f o 1 * ! * fi ' * - f! o 1 * ! * fi ' * - # /#-. o @9=4%> 4 @9=4%! % o 6@:4%> 4 @9=4%! %; o 6@:4%> 4 #%! 0/##-/!010&. # o 66; 4f 0 /1#! /#-. @9= o @9=4 0 2- 1. 7d04 * 4( 6:* > e0 f 4 !4 4 %> 4 e%f december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 19 advance information #*)3#456 78 1 " 9 % #$ # #$$ # % #$ ' -$ ' ' % 0 ' : -$ ' -$ 7d0@9=#%; f 0 f!0 7 ; @ d # 6 7; e9<42, 6 6;<42, 8/6@/6@ 6d7* # @ f @ #*)3#456 /8 1 " 9 % #$ # #$$ # % #$ ' -$ ' ' % 0 ' : -$ ' -$ 7d0@9=#% f 0 f!0 7 ; @ d # 6 7; e9<42, 6 6;<42, 8/6@/6< 6d7* # @ f @ #*)3#456//8 1 " 9 % #$ # #$$ # % #$ ' -$ ' ' % 0 ' : -$ ' -$ 7d0@9=# f 0 f!0 7 ; @ d # 6 7; e9<42, 6 6;<42, 8/6@/6< 6d7* # @ f @ 0* & * 8 39# : %: % ; < : * % % 8 1( * ( * - ) 0* & * 8 39# : %: % ; < : * % % 8 1( * ( * - ) 0* & * 8 39# : %: % ; < : * % % 8 1( * ( * - ) 20 s73ws256n based mcps s73ws256n_00_a3 december 16, 2005 advance information 7 physical dimensions 7.1 tld137137-ball fine-pitch ball grid array (fbga) 9 x 12.0 mm package 3393\ 16-038.22a package tld 137 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 10.40 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 14 matrix size d direction me 10 matrix size e direction n 137 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement g5,h5,h6 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. pn ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 137x a1 a2 a 0.15 m c 0.08 m c ab pin a1 december 16, 2005 s73ws256n_00_a3 s73ws256n based mcps 21 advance information 7.2 ftf137137-ball fine-pitch ball grid array (fbga) 9 x 12 .0 x 1.4 mm package 3532 \ 16-038.21 \ 12.13.05 package ftf 137 jedec n/a d x e 12.00 mm x 9.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.17 --- --- ball height a2 1.02 --- 1.17 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 10.40 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 14 matrix size d direction me 10 matrix size e direction n 137 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement g5,h5,h6 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 137x 0.15 m mc cab 0.08 b c c bottom view 7 se e1 d1 ed 10 8 6 7 9 5 3 4 2 1 ee pin a1 corner 7 sd b pn g ml k jh fedc a a d e c 0.15 (2x) b c 0.15 (2x) c 9 top view side view pin a1 corner 6 a1 a a2 index mark 0.08 0.20 + % + + + publication number s29ws-n_m0 revision i amendment 0 issue date december 3, 2005 general description @80@9=e6@: 4 ! 66; ! ) ), ) * - :; 42, 1 (( 67 1 689 1 - q ) + * ) ) distinctive characteristics # (;<8 9$ 9 (;*7=(;>58 ((7 %?-" # 93 $ @"a )4+@ 3 % #b+ ' " (69< @ 3#4569(4<c $ (6,@ "$ 45d9(466d,@ 3#4569(4< <9 (69)4 @" @" @ $ # ## (4< @ " 47+ $ / (77c777 $ $ .$ $ @"e/ / d4;d ! @ 3f $ $ $ 1@8 @ " @ " # 3 $ $ $ $ # $ / $ 2'%$ $ $ #" " $ $ c $ $$ $ #$$ " performance characteristics s29ws-n mirrorbit tm flash family s29ws256n, s29ws128n 256/128 megabit (16/8 m x 16 bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory data sheet preliminary - #$ 0$ !a <7665d 4/ ' (( :;:;:; 4/ f f (( 8 66@ 6d9 4/ (( :;:;:; 4/ (( @;@;@; 4/(m ( :;:;:; 4/$m $ 6d9 6d9 6d9 $ $ ( f > h:;42, d: $ 9; 68 68 4 @;r -$ :/ - 0 <;r 0 f 1 (( 0 8<r 0 f 1 (( 0 =r 6=k) 69; =<k) =;; december 3, 2005 s29ws-n_m0_i0 23 preliminary 8 input/output descriptions & logic symbol : 6 - table 8.1 input/output descriptions symbol type description @da ; 0@9=# @@* ;06@: %369a%3; e$ % e (m ( ('k $m $ ('k 0m 0 1 (( % ) 1 e$ i #( #( # >%l $ > ) ('k ( - ) + ('k 1%m 1 0 ) p) ) / - 0 >m 2) > ')o 0 m 0 1 ' 1 2 (( 1 22 p - 1 ' 1 2 >!j > > 4( -* )4( 24 s29ws-n_m0_i0 december 3, 2005 preliminary 9 block diagram figure 9.1. s29ws-n block diagram e$ f s*% l*% ( $ ' 1 i i41 i 1 (( % ( ( > 1 (( 1 0m >m 0 m (( (m $m %369 = %3; % ' l*i ( 4/ ' / a ;t >%l f >%l f ( f ( 1%m ('k t 0@9=#. @d* ; 06@:#. @@* ; december 3, 2005 s29ws-n_m0_i0 25 preliminary 10 additional resources 1 ))) ) . $$ j $ f 4%% j f 4 !4 % > e0 e> 4fu!4 0 f f > % * 0 ) ( ! 1 6<1 / #$ % ( #@ #$$ )* ! ! #$$ 12%' 1 f $>( % -" #$$ ( ''( . j.<;:7<8*97;d v ;d9d@@*dd@< #$ 111 869% i % $f/d<9d ( 8<;::*d<9d j .<;:*8=@*@9;; 6*:==* # $# v ' ( *k)-8!e6;! 6*6<# * k)-*- k)-* k ) @6;*;;@< v .;<<*@@d*67;; 26 s29ws-n_m0_i0 december 3, 2005 preliminary 11 product overview @80*# @9= 6@: 4 6: * e) ! , q) ) ) , 6=:4) 6= :* 6=* d@*) )) ) ) d@*) * ) e . + @9=) $ 11.1 memory map @80@9=e6@:#4 6= - , ) 6 6 6 a 66@ 0 % / > * ? #&&(= #&+@/ % % a >% bc3 / >>&&&&&=>> table 11.1 s29ws256n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes @4f < d@ ; ;;; ;;;;;;a;;d!!! ( ;;6 ;;<;;;a;;7!!! ;;@ ;;:;;;a;;f!!! ;;d ;;(;;;a;;!!!! 69 6@: ;;< ;6: ;6;;;;a;6!!!!;!;;;;a;!!!!! 6@:kf //;;;;a//!!!! @4f 6= 6@: 6 ;68 ;d< 6;;;;;a6;!!!!6!;;;;a6!!!!! @4f 6= 6@: @ ;d9 ;9; @;;;;;a@;!!!!@!;;;;a@!!!!! @4f 6= 6@: d ;96 ;== d;;;;;ad;!!!!d!;;;;ad!!!!! @4f 6= 6@: < ;=7 ;:@ <;;;;;a<;!!!! @98 !!<;;;a!!7!!! @=; !!:;;;a!!f!!! @=6 !!(;;;a!!!!!! december 3, 2005 s29ws-n_m0_i0 27 preliminary 0 % / > * ? #&&(= #&&d@/ % % a >% bc3 / >>&&&&&=>> table 11.2. s29ws128n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 64f < d@ ; ;;; ;;;;;;a;;d!!! ( d@ ;;6 ;;<;;;a;;7!!! d@ ;;@ ;;:;;;a;;f!!! d@ ;;d ;;(;;;a;;!!!! 7 6@: ;;< ;6; ;6;;;;a;6!!!!;7;;;;a;7!!!! 6@:kf //;;;;a//!!!! 64f : 6@: 6 ;66 ;6: ;:;;;;a;:!!!!;!;;;;a;!!!!! 64f : 6@: @ ;68 ;@= 6;;;;;a6;!!!!67;;;;a67!!!! 64f : 6@: d ;@7 ;d< 6:;;;;a6:!!!!6!;;;;a6!!!!! 64f : 6@: < ;d9 ;<@ @;;;;;a@;!!!!@7;;;;a@7!!!! 64f : 6@: 9 ; 28 s29ws-n_m0_i0 december 3, 2005 preliminary 12 device operations e) -* ! $ ) + ) 676 67@ p ) / * 0 ) + - ) ) ) 12.1 device operation table 6 @ 6 + table 12.1 device operations ee&fe4! g 26h2 6h 12.2 asynchronous read + ) ) * ) * / a ; ) 1%m (m1 ' 0m 1 2 1%m $m 1 ' 1%m 1 2 % e%369* e%3; $ $m operation ce# oe# we# addresses dq15C0 reset# clk avd# > * ' ' ' 2 %$ 2 s > * ' ' 2 %$ 2 s ' 0 ' 2 ' e$ 2 s ' 0 ' 2 ' e$ 2 (m 2 s s s 2 i2w 2 s s 2) > s s s s 2 i2w ' s s burst read operations (synchronous) ' f ' s 2 s 2 f / ) % %f '' 2 s f %$ 22 f 2 s 2 s 2 i2w 2 s f >m s s 2 s 2 i2w ' s s f ) f ' s 2 e$ 2 december 3, 2005 s29ws-n_m0_i0 29 preliminary 12.3 page read mode ) 4->$4 ) (( ( + ) + (( 0 (m o 1 2 (m + (( ( 2 (m $m ! - / a @ 6 a ; )) / a @ <*) 6 a ; ) ) ) * ) 6@@ ) ) * # + - > 5 ) * - * * ) * * ) - * / ) * ) / * - * * ) * * ) - * * 1%m ) (( - 1%m) ) 6.; % $ $ * * e(m e 1%m) $ 12.4 synchronous (burst) read mode & configuration register 0 5 ) + + , - ) * 6@<6 6@<@ 6@<d ) * ) $ ( > ) ) (( table 12.2 word selection within a page 3 ( 7 0; ; ; 06 ; 6 0@ 6 ; 0d 6 6 30 s29ws-n_m0_i0 december 3, 2005 preliminary ) ) >%l > ( > + ) + 6@<< ( > 6 7 6 4 ( figure 12.1. synchronous/asynchronous state diagram ) 5 ) . (( . - (>6da(>66. - ) (( + ) f (( - ) 5 ) . .) ) x6.;y;; * * ) ) ) + ) ) ** ) x6.;y;6 6; 66 . 6@:) $ ) ) - + ) - + . ) / 2 + ) ) )) >%l ) / 6 @ d * 6@: ) + @80@9=e6@:# > ( * > (>66*(>6< power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (cr15 = 0) set burst mode configuration register command for asynchronous mode (cr15 = 1) december 3, 2005 s29ws-n_m0_i0 31 preliminary table 12.3 address latency (s29ws256n) table 12.4 address latency (s29ws128n) table 12.5 address/boundary crossing latency (s29ws256n @ 80mhz) table 12.6 address/boundary crossing latency (s29ws256n @ 66 mhz) table 12.7 address/boundary crossing latency (s29ws256n @ 54mhz) table 12.8 address/boundary crossing latency (s29ws128n) 3 3 # ; /) %;%6%@%d%<%9%=%7%: 6 /) %6%@%d6)%<%9%=%7%: @ /) %@%d6)6)%<%9%=%7%: d /) %d 6) 6) 6) %< %9 %= %7 %: 3 3 # ; 9 = 7)%;%6%@%d%<%9%=%7%: 6 9 = 7)%6%@%d6)%<%9%=%7%: @ 9 = 7) %@ %d 6) 6) %< %9 %= %7 %: d 9 = 7) %d 6) 6) 6) %< %9 %= %7 %: 3 3 # ; 7) %;%6%@%d6)6)%<%9%= 6 7) %6%@%d6)6)6)%<%9%= @ 7) %@ %d 6) 6) 6) 6) %< %9 %= d 7) %d 6) 6) 6) 6) 6) %< %9 %= 3 3 # ; =) %; %6 %@ %d 6) %< %9 %= %7 6 =) %6%@%d6)6)%<%9%=%7 @ =) %@ %d 6) 6) 6) %< %9 %= %7 d =) %d 6) 6) 6) 6) %< %9 %= %7 3 3 # ; 9) %;%6%@ %d %<%9%=%7%: 6 9) %6%@%d6)%<%9%=%7%: @ 9) %@%d6)6)%<%9%=%7%: d 9) %d 6) 6) 6) %< %9 %= %7 %: 3 3 # ; 9 = 7)%;%6%@%d6)%<%9%=%7 6 9 = 7) %6 %@ %d 6) 6) %< %9 %= %7 @ 9 = 7) %@ %d 6) 6) 6) %< %9 %= %7 d 9 = 7) %d 6) 6) 6) 6) %< %9 %= %7 32 s29ws-n_m0_i0 december 3, 2005 preliminary figure 12.2. synchronous read (4;d;( % + ) ;;;;;;) * (m >o1 ' ( 1%m) ) 6@:*) * + ) + 6 @ 6 ; - ) + - - j )* 1%m write unlock cycles: address 555h, data aah address 2aah, data 55h write set configuration register command and settings: address 555h, data d0h address x00h, data cr load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait x clocks: additional latency due to starting address, clock frequency, and boundary crossing end of data? yes crossing boundary? no yes completed delay x clocks unlock cycle 1 unlock cycle 2 ra = read address rd = read data command cycle cr = configuration register bits cr15-cr0 note: setup configuration register parameters no " e * december 3, 2005 s29ws-n_m0_i0 33 preliminary (4;d;4 <+c(6+c)4+3 1 % @"3 $ / ): 6= d@) ) ) , ) + 6 @ 8 ! / :*) d( ) d:*d! + ) d(*d%*d*d!*d:*d8*d *df * ) ) ) 6=*) d@*)' 0 + ) - . % * / * b * table 12.9 burst address groups (4;d;) <+c(6+c)4+3 1 % @"3 $ ) :*) 6=*) d@*) / / ) : 6= d@ ) ! / :*) d( ) d8*<; + ) d(*d%*d*d!*<;*<6*<@* ) 1%m # 6@: ) ) ) ) (4;d;d ) j ) * ) * / ( > * + (m ( > * + 676 ) mode group size group address ranges :*) :) ;*7 :*! 6;*67 6=*) 6=) ;*! 6;*6! @;*@! d@*) d@) ;;*6! @;*d! <;*9! 34 s29ws-n_m0_i0 december 3, 2005 preliminary table 12.10 configuration register " 0 ) * * + 6 7 6 + ) + % # % (>69 % > 4 ;o > f 4 6o > 4 (>6< > 6o@80@9=#=70 ;o 5d !a 66 "a <7 !a (>6d 0 @806@:# ;66 ;66o% 9 ('k 6;;o% = ('k 6;6o% 7 ('k 66;o> 666o> ) ) # 6 @ @80@9=# (>6@ @806@:# 6;; @80@9=# (>66 @806@:# 6;6 @80@9=# (>6; >%l ;o>%l ) 6o>%l (>8 > 6o (>: >%l ;o>%l - 6o>%l ) 0 (>6d*(>66 ;;; >%l ) (>: (>7 > 6o (>= > 6o (>9 > ;o (>< > ;o (>d f 0 ;o#0 f 6o0 f (>@ (>6 (>; f ' ;;;o( ;6;o:*0' f ;66o6=*0' f 6;;od@*0' f " 0 ) b 8 % " * 3 " % % ) " december 3, 2005 s29ws-n_m0_i0 35 preliminary 12.5 autoselect % % * + ) * * 0 6 @ 6 6 z ) - ) - ) / + ) ) - * * ) ) ) * * -) 6 7 6 + table 12.11 autoselect addresses description address read data 4 % f c;; ;;;6 % % 06 f c;6 @@7 % % 0@ f c; @@d;0@9=# @@d606@:# % % 0d f c;! @@;; f # f c;d %369*%3:o> %37! ' -f.6o' - ;o#' - %3=( ' -f.6o' - ;o#' - %392 - f.6o> ;o 2 - %3< %3d0 m f( .;;o0 m f f f ;6 6; 66o> %3@o> %36%lf ) x' -> %3 %3; f x' -> %3dy.6o ) ;o f -' -e j - c;@ ;;;6o' - ;;;;oj - , b. , &-7!' !'& / 36 s29ws-n_m0_i0 december 3, 2005 preliminary # * / : 3#3 :# 0 : 8 ) ) ( / * %> ee / !/ i g 9 ))) ))) 5 ! ) /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)bank_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ software functions and sample code table 12.12 autoselect entry ''%! o[ ( cycle operation byte address word address data j -( 6 0 f / f /999 ;/;; j -( @ 0 f /999 f /@ ;/;;99 ( 0 f / f /999 ;/;;8; table 12.13 autoselect exit ''%! o[ /( cycle operation byte address word address data j -( 6 0 csss csss ;/;;!; december 3, 2005 s29ws-n_m0_i0 37 preliminary 12.6 program/erase operations ) ) 2) 6@8 ! ) + 1%m (m1 ' $m1 2 ) 0m (m1 ' $m1 2 ) ) 0m(m ) 6 0m(m # ) . 0 %37%3=> 0 $ ";& -"6& %39 o6 + ) ";&$ ";&"6& ) / (! ) * ) + ) + )* (4;6;( # 3 ) ! ) ! * :* 6=*d@*) 0 0 f * 676 + ! 6@d ) 0 * %37%3=> 0 $ % / (! ) 38 s29ws-n_m0_i0 december 3, 2005 preliminary ) * + figure 12.3. single word program write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) fail. issue reset command to return to read array mode. perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = done? error condition (exceeded timing limits) pass. device is in read mode. december 3, 2005 s29ws-n_m0_i0 39 preliminary 3 3 # ) ( / ) > ee / !/ i g 9 ))) ))) 5 ! ) /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ (4;6;4 3 % 0 f ) ) / d@) * ) ")& 0 f + ) ) - ) ) 0 f ' ) ) ) ") 6& ) ) ) ) ) / " f !& * / , ) # o 6! /* = ;9 ) ) e e ") * * & * + e ) *) * * ") * * & 4 s * 9 ") * * & e ) 0 f ") * * & 0 f * ") * * & f$> ) e% ) e ) # 0 f " e& " f !& ) z ) * #$ + ) * software functions and sample code table 12.14. single word program ''%! o[ ( cycle operation byte address word address data j -( 6 0 f c f c999 ;; j -( @ 0 f c99< f c@ ;;99 0 f c f c999 ;; ; 0 0 0 %0 40 s29ws-n_m0_i0 december 3, 2005 preliminary * $ ) ) " f !& e) 0 f * " & %f + ) ) * %37 %3= %39 %3@ %36 0 f ) * " & * e j 0 f > % 0 f + f$>% ) . ' , "# ' & 0 0 *f *' 0 e% ) * * " & ") & 0 "( ( & "& * f$> %36o6 %37o% m " & %3=o$ii' %39o; 0 f $ ) f$>% "0 **f * & + + ) ) j -f # (! ) 0 ) + ) ) ) j ) ) ) 0 / * ) december 3, 2005 s29ws-n_m0_i0 41 preliminary 3 3 # e e * % % % * %* %-)+ ) %>%% * %% % ?. @ ) ( / ) > ee / !/ i g 9 ))) ))) 5 ! ) /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (uint16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ software functions and sample code table 12.15. write buffer program ''%! j o[0 f ( [ f !( cycle description operation byte address word address data 6 j - 0 f c f c999 ;; @ j - 0 f c99< f c@ ;;99 d 0 f '( 0 ;;@9 < 0 0( 0 0( #a6 @ "@ ()4@ ; 9d= 'f 0# 0 0# 0# ' 0 f ! 0 ;;@8 42 s29ws-n_m0_i0 december 3, 2005 preliminary figure 12.4. write buffer programming operation (4;6;) # / 676 4 ( p ! 6@9 $ * + , ) !!!! + write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: address 555h, data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes no no no no wc = 0? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. pass. device is in read mode. confirm command: sa = 0x29h wait 4 s (recommended) perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command december 3, 2005 s29ws-n_m0_i0 43 preliminary + ) * % * * ) ' + ) ) / * * - %3d %3d. * 0m + 0 - # ) * - %37%3=e%3@ -> 0 $ $ 2) ) + - ! 6@9 > ) ( / > ee / !/ i g 9 ))) ))) 5 * ! ) /* example: sector erase command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ software functions and sample code ta b l e 1 2 . 1 6 . s e c t o r e r a s e ''%! o[ ( cycle description operation byte address word address data 6 j - 0 f c f c999 ;; @ j - 0 f c99< f c@ ;;99 d ( 0 f c f c999 ;;:; < j - 0 f c f c999 ;; 9 j - 0 f c99< f c@ ;;99 = ( 0 ;;d; 2 g @ @" #/ ; 44 s29ws-n_m0_i0 december 3, 2005 preliminary figure 12.5. sector erase operation no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s (recommended) perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? timeout resets after each additional cycle is written ? the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data 0 + %% 8 !') % % ! 6@= december 3, 2005 s29ws-n_m0_i0 45 preliminary (4;6;d "$/ #h ( /* 6 7 6 - ) + , !!!! + * "( % & /) + + 0 - * %37%3=e%3@> "0 $ & ) 2) * ) + - ) ( / > ee / !/ i g 9 ))) ))) 5 * ! ) /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ (4;6;5 / # $ 9/ 0 ) * * * ) - + ) ) * * + ) software functions and sample code table 12.17. chip erase ''%! o[( ( cycle description operation byte address word address data 6 j - 0 f c f c999 ;; @ j - 0 f c99< f c@ ;;99 d ( 0 f c f c999 ;;:; < j - 0 f c f c999 ;; 9 j - 0 f c99< f c@ ;;99 = ( ( 0 f c f c999 ;;6; 46 s29ws-n_m0_i0 december 3, 2005 preliminary 0 ) * / * + / ' ) ) - * * * " & > ) * %37*%3; %37 %3= %3@ * > 6 @ @ = * - * * * %37 %3= 5 * * + > "0 f $ & " ( * + & ) > - * - + ) ) ! ) > ) ) ( / > ee / !/ i g 9 ))) ))) 5 ! ) /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ ) ( / > ee / !/ i g 9 ))) ))) 5 ! ) /* example: erase resume command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ software functions and sample code table 12.18. erase suspend ''%! o[ ( cycle operation byte address word address data 6 0 f - f - ;;f; ta b l e 1 2 . 1 9 . e r a s e r e s u m e ''%! o[ > ( cycle operation byte address word address data 6 0 f - f - ;;d; december 3, 2005 s29ws-n_m0_i0 47 preliminary (4;6;6 # $ 9 ) * "0 f & * 0 ) * ) ' " z* &) ) * * ) + / ) + ) ) 0 / " ( + & > ) %37%3= 5 "0 $ & ) > " z & / ! ) > ) * ) ( / > ee / !/ i g 9 ))) ))) 5 ! ) /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ ) ( / > ee / !/ i g 9 ))) ))) 5 ! ) /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ software functions and sample code table 12.20. program suspend ''%! o[ ( cycle operation byte address word address data 6 0 f - f - ;;f; ta b l e 1 2 . 2 1 . p r o g r a m r e s u m e ''%! o[ > ( cycle operation byte address word address data 6 0 f - f - ;;d; 48 s29ws-n_m0_i0 december 3, 2005 preliminary (4;6;* 9"$/ ) ) (( + -" "$$ " (7 $ ; @9 ( 6; ( 1 22 j * -f + 0 f ' * + j -f # "0 **f * > & + ) j -f d* > + > 1 22 (( * - ((1 22 (( 1 22 * (( p (( - 1 ' p (( 1 2 (4;6;< 2'%$ j -f ) $ * j -f )) + ) ) - + * + "( % & ) + - + % - > j -f j -f> / - )* * - + - 8; ;; - ) ( / - / > ee / !/ i g 9 ))) ))) 5 ! ) software functions and sample code table 12.22. unlock bypass entry ''%! o[j -f ( cycle description operation byte address word address data 6 j - 0 f c f c999 ;; @ j - 0 f c99< f c@ ;;99 d ( 0 f c f c999 ;;@; december 3, 2005 s29ws-n_m0_i0 49 preliminary /* example: unlock bypass entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)bank_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; (4;6;> 3 0$ # ) %36 %3@ %3d %39 %3= %37 %m %37 ) * ) - %m 0m * + # %m ) ) * * 0 f > %m ) ) ) * * % %37 %37%37 0 %37 %37 ) %m %37 /* - % %m ";& %370 * - %m "6& %37 ) %37 table 12.23. unlock bypass program ''%! o[j -f ( cycle description operation byte address word address data 6 ( 0 f c/// f c/// ;; ; @ ( 0 % ta b l e 1 2 . 2 4 . u n l o c k b y p a s s r e s e t ''%! o[j -f> ( cycle description operation byte address word address data 6 > ( 6 0 f c/// f c/// ;;8; @ > ( @ 0 f c/// f c/// ;;;; 50 s29ws-n_m0_i0 december 3, 2005 preliminary + ) %m %37 / - 2) %37 ) v %37 * )%3=*%3;) $ $ m ) %37% ) %37 %37 %3=*%3; 1 %37*%;; ) . 6@@= 0 $ ) %m %37 ! 6@= 0 $ !) ) %m * p ! 6=6: %m % ) %m december 3, 2005 s29ws-n_m0_i0 51 preliminary figure 12.6. write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1) dq6 is toggling if read2 dq6 does not equal read3 dq6. 2) dq2 is toggling if read2 dq2 does not equal read3 dq2. 3) may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4) write buffer error if dq1 of last read =1. 5) invalid state, use reset command to exit operation. 6) valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5) 52 s29ws-n_m0_i0 december 3, 2005 preliminary f %3= ) * ) f - 0m + * % * %3= 0 %3= + ) %3= / x y %3= %3@ ) * 0 %3= 0 %3=* 2) %3@ ) * %37 %37.%m ) %3= / + ) %3= * * * ) . ! 6@= 0 $ !) p !* 6=68 f % 6@@9 6@@= f %3= + $m(m * ) " f & %3@ ) )%3= ) * ) * f 0m + %3@ ) ) f %3@ ) * %3= ) ) + > 6@@9 %3@ %3= ) . ! 6@= "%3=. f & ! 6=6: a 6=@9 december 3, 2005 s29ws-n_m0_i0 53 preliminary table 12.25. dq6 and dq2 indications 0 %37a%3; ) ) ) * ) ) ) ) * %37a%3; ) 2) ) ) %39 %39 ) * 5 %39) ) %39 %39 * - ) > !* 6@= 0 ) e - %3= %3@ ) ) * ) - - %37 ) % %3@%3= (m ) 1%m )2 * + 1%m) (m * ! 6=@6 6=@< if device is and the system reads then dq6 and dq2 ) ) ) ) 54 s29ws-n_m0_i0 december 3, 2005 preliminary ! ! %39 ) / j %39 "6 & ) "6& %39 "6& ) ";&$ ";& -"6 &j ) / %39 "6&j ) * * -) * * "# $ $!%# $ ) + %3d ) * 0 * %3d) ";&"6& ) %3d ( + ) %37%m %3= f + %3d %3d"6 & p * / %3d"; & * ) - %3d ) * + %3d - 6 @ @ = ) %3d &'$%(($)*$ %36 ) 0 f ) j %36 "6& 0 f > + 0 f * $ december 3, 2005 s29ws-n_m0_i0 55 preliminary table 12.26. write operation status !'( jg % 5%% > %>%%% % " !'(% % !'+ !' 8 / % " ) ! / 5% 7 !' , 3 #3h"0 , 3 5%% ( 0 % , 3 5%% . !'+ , 3 5 %% !'+ ($+)#,) ' - .// ) ## - * % 8 % !' 6!'- status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) 4 %37m ; #e # ; ; ; 6 #e 4 # d > ) #1 ' % ?. # @ #1 ' % ?. # @ #1 ' % ?. # @ #1 ' % ?. # @ #1 ' % ?. # @ #1 ' % ?. # @ > ) # * % % % % % % 4 # = * * > 6 # ; #e #e # * % % % % % % * * %37m ; #e #e #e 0 f # 9 fjl %37m ; #e #e ; / ' %37m 6 #e #e ; f$> %37m ; #e #e 6 56 s29ws-n_m0_i0 december 3, 2005 preliminary 12.7 simultaneous read/write e) ) - * ) - ) - / ! 6=@8 f -**f -> e0 ( )) ) ), > %(( * (4$( *) * *) * 12.8 writing commands/command sequences 0 ) ) ('k 0 ) ('k 1%m % ) ) + ) 1%m (m1 ' $m1 2 ) 0m (m1 ' $m 1 2 ) ) % ) (m 0m1 ' $m1 2 ) 0m(m ) 6 0m(m 6 6 6 a 66@ / -.f -6 6< =<k) ) f -; 69 6=k) =<k) " - & + + - " & + + ((@ "%(( & * ) " (( * & " (( * & ) 12.9 handshaking - ) ) * >%l> ) (m 0 $m) * ) >%l 6; ( > (>6da(>66 ( > ) 6 @ 6 ; ( > f: ( > ) ) >%l december 3, 2005 s29ws-n_m0_i0 57 preliminary 12.10 hardware reset >m ) 0 >m ) > e ) >m ) + 0 >m 1 )(4$ ((< >m 1 ' 1 >m ) * ) ! ! 6=9 6=6d 12.11 software reset ) 6 7 6 ) . 6 / @ ) %39 ) ) d / -e - < * * ) 9 3 3 # ) ( / > e e / !/ i g 9 ))) ))) 5 * ! ) /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; ) ) . - > $ * ) ) + -) * )) software functions and sample code table 12.27. reset ''%! o[> ( cycle operation byte address word address data > ( 0 f c/// f c/// ;;!; 58 s29ws-n_m0_i0 december 3, 2005 preliminary + ) - ) - * * ) + - ) ) - * * %36 0 f ) \0 f > \ + > > )- / - )* - * + x y december 3, 2005 s29ws-n_m0_i0 59 preliminary 13 advanced sector protection/unprotection ej ) e) ) ) ) ! 6d6 figure 13.1. advanced sector protection/unprotection hardware methods software methods acc = v il ( all sectors locked) wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 6,7,8 6. 0 = sector protected, 1 = sector unprotected. 7. protect effective only if ppb lock bit is unlocked and corresponding ppb is ?1? (unprotected). 8. volatile bits: defaults to user choice upon power-up (see ordering options). 4. 0 = sector protected, 1 = sector unprotected. 5. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset. 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock. 3. n = highest address sector. 60 s29ws-n_m0_i0 december 3, 2005 preliminary 13.1 lock register ) ) ) %lf ) ";& ) ) * * - . ' -> 4 ' -f%36 ' -> ) 4 ' -f%3@ table 13.1 lock register ! - 6 7 @ 6 ) ) * - @ ' -> f( + ) ) f -; ) - ) / d - , < $ )4 ' -f 4 ' -f * ) * 4 ' -f )4 9 % e ) = 0 - f - ) - - %lf ) * 7 ' - . % - + + # -; <*r -) + * ) / f> - ) - * ( ' -> device dq15-05 dq4 dq3 dq2 dq1 dq0 @80@9=# 6 6 6 ) 4 ' -f 4 ' -f ( f @806@:# j %lf' -ff ;o ) 6o ) f$ * f ;o f 6o f ) 4 ' -f 4 ' -f f december 3, 2005 s29ws-n_m0_i0 61 preliminary ) . 6 * : f - ) ) ) @ !* % * : ) d i : e 6d@ a 6d= 13.2 persistent protection bits f + * ! + 6 f @ f e .> - * ) f e d ) - < > ) - f 9 > = @d* 6<0@9=# @@* 6<06@:# ) 7 f' -f f / * ) f : f + 8 / / ) * ) f -; 6; f ) f > ( ) ) ! 6d@ 62 s29ws-n_m0_i0 december 3, 2005 preliminary figure 13.2. ppb program/erase algorithm read byte twice addr = sa0 enter ppb command set. addr = ba program ppb bit. addr = sa dq5 = 1? yes yes yes no no no yes dq6 = toggle? dq6 = toggle? read byte. addr = sa pass fail exit ppb command set dq0 = '1' (erase) '0' (pgm.)? read byte twice addr = sa0 no wait 500 s december 3, 2005 s29ws-n_m0_i0 63 preliminary 13.3 dynamic protection bits % f + %lf f "6&f %lf ( + %lf * ";& "6& )) * ) 6 %lf ";& "6& 0 f "6& ) %lf @ %lf ) "6& f 6 d @ d ) %lf ) ";& < - ) 9 %lf ( 2) * - ) + ! f' -f ) * ) f f' -f - f = / f' -f 0 mo1 ' # f %lf ) ((o1 22 ) ((o1 2 13.4 persistent protection bit lock bit f' -f 0 * ";& - f ) "6& ) f f' -f 6 #) + - )* p ) ) * @ f' -f ";& f 13.5 password protection method ) 4 ) * 4 + =<) - f' -f ) + ) f' -f ";& ) / )j - * ) f' -f ) f 64 s29ws-n_m0_i0 december 3, 2005 preliminary 6 + )$ * )) )4 ' - f @ ) ( ";& "6& ";& * ) ";& d )"6&) < =<*) ) 9 ) ) = )4 ' -f =<*) ) 7 )4 ' -f : ) ) 6a ; )> ) )j - 8 / ) - 6; )j - 6r - =<* ) 66 / 6r + - =<*) 6@ ) ) ) 6d ) 6< ) )4 ' -f ) f' -f 69 + ) f -;> ) - / f -; ) 6= 67 ) 6: %lf f f' - ) %lf f f' - december 3, 2005 s29ws-n_m0_i0 65 preliminary figure 13.3. lock register program algorithm write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock register can only be progammed once. wait 4 s (recommended) pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array. 66 s29ws-n_m0_i0 december 3, 2005 preliminary 13.6 advanced sector prot ection software examples 6d@ %lf f f' -f f' -f - ";& f ) f' -f - "6& ) ) ! 6d6 ) 13.7 hardware data protection methods ) ) . 0 0 m1 ' - 0 ((1 ' - ) * ) ) . ();*;( 3f " 0 ) 0 m * ej 1 ' 0 m " & ) ** 1 2 0 m ) ) * ) ) # 0 m 0 m + / ();*;4 " / $ (( 1 ' table 13.2 sector protection schemes unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status ; ; / f ; ; / f ; 6 6 j ; 6 ; %lf 6 ; / f 6 ; / f 6 6 ; %lf 6 6 6 j december 3, 2005 s29ws-n_m0_i0 67 preliminary ();*;) 1@8 3 " 0 1 (( 1 'k$ ) * 1 (( ) * ) *) e + ) 1 (( 1 'k$ ) ) 1 (( 1 'k$ ();*;d 3 i&" j # d $ m (m0m ) ();*;5 @ +2$3 " 0mo(mo>mo1 ' $mo1 2 ) 0m ) * 68 s29ws-n_m0_i0 december 3, 2005 preliminary 14 power conservation modes 14.1 standby mode 0 ) $m (4$ ) (m >m 1 (( ];@1 + ( * ) ((d "%(( & 14.2 automatic sleep mode , ! ) ) (( c@; (m 0m $m * )) 0 ) 0 # ) + ) ((= %(( (4$( * 14.3 hardware reset# input operation >m ) 0 >m ) > e ) >m ) + 0 >m 1 ];@1 )(4$ ((< >m 1 ' ) 1 ];@1 >m ) ! * ) ! 14.4 output disable (oe#) 0 $m 1 2 december 3, 2005 s29ws-n_m0_i0 69 preliminary 15 secured silicon sector flash memory region /! # # @9= ) 6@:) 6@:) * @9=*) ! f %37 ;d ) ! - ) ( f%3= ) ( - ) ) . 0 ) / f -; $ ) * ) ) > f ) ) !! - ;; > ; ( / ; $ ( / / 4 ) / * table 15.1 secured silicon sector addresses 15.1 factory secured silicon sector ! ) ) ! f%37 "6& - # ) ) . :0 # ) ! ( ) ( * f # ( * z )) # ) ! ( - ( sector sector size address range ( 6@:) ;;;;:;*;;;;!! ! 6@:) ;;;;;;*;;;;7! 70 s29ws-n_m0_i0 december 3, 2005 preliminary 15.2 customer secured silicon sector ( %3= ";& ) , + ( ! ) . $ ( ( f "6& ( * - ( - ) - - ( ( ) (( - ) ( f -6 69 $ ( - ) / > + ) * ; 15.3 secured silicon sector entry/exit command sequences * * + * / + ( % x ( / 6 7 6 + + ( ) ) / > ) + ;) / + ) ) ( / / > ee / !/ i g 9 ))) ))) 5 ! ) software functions and sample code december 3, 2005 s29ws-n_m0_i0 71 preliminary 3 3 # /* example: secsi sector entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secsi sector entry cmd */ 3 3 # /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ 3 3 # /* example: secsi sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secsi sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secsi sector exit cycle 4 */ table 15.2. secured silicon sector entry ''%! o[ ( cycle operation byte address word address data j -( 6 0 f c f c999 ;; j -( @ 0 f c99< f c@ ;;99 ( 0 f c f c999 ;;:: table 15.3. secured silicon sector program ''%! o[ ( cycle operation byte address word address data j -( 6 0 f c f c999 ;; j -( @ 0 f c99< f c@ ;;99 0 f c f c999 ;; ; 0 0 0 %0 table 15.4. secured silicon sector exit ''%! o[ /( cycle operation byte address word address data j -( 6 0 f c f c999 ;; j -( @ 0 f c99< f c@ ;;99 /( 0 f c f c999 ;;8; 72 s29ws-n_m0_i0 december 3, 2005 preliminary 16 electrical specifications 16.1 absolute maximum ratings - a=9b(c69;b( ) ) a=9b(c6@9b( 1 )> i . e$ / )# 6 a;911 (( c;91 1 (( # 6 a;91c@91 ((# @ a; 91c891 $ ( ( # d 6;; $ %%!/ 26h =& (1! / 26h %* 1 = &1 & - $>%%!/ 26h 1 k&(1! / %*/ 1 k &1 & - $ %%! / # &(1! / #%* / 1 = &1 & - $>%%! / # kd(1%*/ &(1 & ) .% %* % ! 7 / ;# $>%%" <%* % % / 0 * / * / % > / %>%% > %* / * 0 % #/ % d, b. % 5 % * d, (-. figure 16.1. maximum negative overshoot waveform figure 16.2. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v december 3, 2005 s29ws-n_m0_i0 73 preliminary 16.2 operating ranges 3 3 a@9b(c:9b( #$$8 1 (( 1 c6 7;1c6891 h % * / 16.3 test conditions table 16.1 test specifications test condition all speed options unit $ '( ( ' 5 d; ! > ! d;h9< ==42, @9h:;42, ' ;;a1 (( 1 1 (( e@ 1 $ 1 (( e@ 1 c l device under test figure 16.3. test setup 74 s29ws-n_m0_i0 december 3, 2005 preliminary 16.4 key to switching waveforms 16.5 switching waveforms 16.6 v cc power-up # 1 % % % * d, b.l1 % m16&& n 1 % o 16 && n 8 figure 16.5. v cc power-up diagram parameter description test setup speed unit 1( 1 (( 4 6 waveform inputs outputs ( 2' ( '2 % q( ( ( j - ) % # ( ' 2 2w v cc 0.0 v output measurement level input v cc /2 v cc /2 all inputs and outputs figure 16.4. input waveforms and measurement levels v cc reset# t vcs december 3, 2005 s29ws-n_m0_i0 75 preliminary 16.7 dc characteristics (cmos compatible) $>%%2 1 1 %> % % "!p ) 0 2 * * )(%#6$fah1 2f 7 2 / % % 5% ( ! / % % # k & 0* % 8 2 ) - 1 2f 1 q& 1 1 2e m=&1 + 0 %% %1 # 1 b 1 # 1 ff # $ - (c< -$ b 2 ' '( 1 # o1 1 (( 1 (( o1 (( / ]6 r '$ $ ' - ( @ 1 $j o1 1 (( 1 (( o1 (( / ]6 r ((f 1 (( > ( (mo1 ' $mo1 2 0mo1 2 o: 9<42, @7 9< ==42, @: =; :;42, d; == (mo1 ' $mo1 2 0mo1 2 o6= 9<42, @: <: ==42, d; 9< :;42, d@ =; (mo1 ' $mo1 2 0mo1 2 od@ 9<42, @8 <@ ==42, d@ <: :;42, d< 9< (mo1 ' $mo1 2 0mo1 2 o( 9<42, d@ d= ==42, d9 <@ :;42, d: <: ((6 1 (( > ( d (mo1 ' $mo1 2 0mo1 2 6;42, d< <9 942, 67 @= 642, < 7 ((@ 1 (( 0 ( < (mo1 ' $mo1 2 ((o1 2 1 (( 69r 1 (( @< 9@9 ((d 1 (( ( 9 = (mo>mo 1 (( ];@1 1 (( 69r 1 (( @; 7; r ((< 1 (( > ( = >mo1 ' ('ko1 ' 7; @9; r ((9 1 (( ( > 0 0 = (mo1 ' $mo1 2 ((o1 2 h 942, 9; =; ((= 1 (( ( = (mo1 ' $mo1 2 @7;r ((7 1 (( 4 > ( $mo1 2 (mo1 ' 6@ (( ( 7 (mo1 ' $mo1 2 1 (( o891 1 (( =@; 1 (( 6< @; 1 ' ')1 1 (( o6: 1 a;9 ;< 1 1 2 21 1 (( o6: 1 1 (( a;< 1 (( c;< 1 1 $' $ ')1 $' o6;;r 1 (( o1 (( ;6 1 1 $2 $ 21 $2 oa6;;r 1 (( o1 (( 1 (( 1 1 22 1 :9 89 1 1 'k$ ')1 (( ' -* 1 6< 1 76 s29ws-n_m0_i0 december 3, 2005 preliminary 16.8 ac characteristics (6;<;( 1," a .&&r figure 16.6. clk characterization parameter description 54 mhz 66 mhz 80 mhz unit ('k ('k! + 4/ 9< == :; 42, ('k ('k 4 6:9 696 6@9 (2 ('k2 4 7< =6 9; (' ('k') (> ('k> 4/ d d @9 (! ('k! t clk t cl t ch t cr t cf clk december 3, 2005 s29ws-n_m0_i0 77 preliminary (6;<;4 #" 9% # ec .&&r parameter description 54 mhz 66 mhz 80 mhz unit jedec standard (( ' 4/ :; f (( f 1( -$ % 4/ 6d9 66@ 8 ( ('k # 6 4 9 < (2 2 ('k # 6 4 7 = f%2 %2 # /( -( 4 < d (> ( >%l1 4/ 6d9 66@ 8 $ $ $ 1 4/ 6d9 66@ (w ( 2w # @ 4/ 6; $w $ 2w # @ 4/ 6; ( (m ('k 4 < >%l >%l ('k 4 9 < d9 > (( > ('k 4/ 6d9 66@ :9 ( (m 1%m 4 ; 1( 1%m')('k 4 < 1% 1%m 4 7 1%2 1%m2 4 d ('k 4 - + 4 66642, table 16.2 synchronous wait state requirements b h 3 # h ;6 42,^! + 6< 42, @ 6< 42,^! + @7 42, d @7 42,^! + <; 42, < <; 42,^! + 9< 42, 9 9< 42,^! + =7 42, = =7 42,^! + :; 42, 7 78 s29ws-n_m0_i0 december 3, 2005 preliminary (6;<;) - % / * 0 % %% %* / * 2 * ; k<; k <; k)< : ** *"!p ) 0 / * % figure 16.7. clk synchronous burst mode read da da + 1 da + n oe# data (n) addresses aa avd# rdy (n) clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 5 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z hi-z hi-z 12 3456 7 t rdys t bacc da + 3 da + 2 da da + 1 da + n data (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da + 2 da da + 1 da + n data (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da + 1 da da da + n data (n + 3) rdy (n + 3) hi-z hi-z hi-z da da t cr t avdh december 3, 2005 s29ws-n_m0_i0 79 preliminary % / * 0 % %% %* / * 2 * ; k<; k <; k)< : ** *"!p ) 0 / * % 7 !b=! / % / b % 7 ?& @ figure 16.8. 8-word linear burst with wrap around % / * 0 % %% %* / * : / 2 * ; k<; k <; k)< : ** *"!p ) 0 / * % 7 !=!) / % / b % ? )@ figure 16.9. 8-word linear burst without wrap around dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc t avdh dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc t avdh 80 s29ws-n_m0_i0 december 3, 2005 preliminary % - * 0 " %% 8 "b& / "!p * / figure 16.10. linear burst with rdy set one cycle before data (6;<;d " k " .&&r hf d, b. $ 5d !a 66 !a <7 !a 2 e/ / # ( (m') 4/ :; (( 4/ :; 1% 1%m') 4 : 1% > 1%m 4 < 1%2 2 > 1%m 4 7 = $ $ $ 1 4/ 6d9 $2 $ 2 > 4 ; %m 4 6; $w $ 2w # 4/ 6; ( (m 1%m 4 ; (( 4/ @; $2 $ 2 ! (m $m ) # @ 4 ; (w ( $ 4/ 6; da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 1567 t rdys t bacc t cr ~ ~ ~ ~ ~ ~ ~ ~ t avdh december 3, 2005 s29ws-n_m0_i0 81 preliminary "#" # "!" ! figure 16.11. asynchronous mode read figure 16.12. four-word page-mode operation t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas a0 a1 a2 a3 a1-a0 ce# avd# oe# we# data a22-a2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d0 d1 d1 d2 d3 same page address t ce t acc t oez t pacc t oh t pacc t oh t oe t oez t oh t pacc optional t coez 82 s29ws-n_m0_i0 december 3, 2005 preliminary (6;<;5 ! @ /#/-f .&&r figure 16.13. reset timings parameter description all speed options unit jedec std. > >m 0 4 d; r >2 > 2 f > # 4 @;; reset# t rp ce#, oe# t rh december 3, 2005 s29ws-n_m0_i0 83 preliminary (6;<;6 / 9 - .&&r # * % # * % * * % # * * % ) 2 * % % ,2 * % % ec 7 ; 5%% 5 % < % % ( ! %% % parameter description 54 mhz 66 mhz 80 mhz unit jedec standard 1 1 0( 0 ( # 6 4 :; 10' # @ d 4 9 ; 0' s 2 2 # @ d 4 8 @; 1% 1%m') 4 : %102 % % 4 <9 @; 02%s %2 %2 4 ; i20' i20' > > f 0 4 ; ( (m 1%m 4 ; 022 (2 (m2 4 ; 0'02 0 0 0 4 d; 020' 0 2 0 02 4 @; >e0 ' f ) > 0 $ 4 ; 1 % 1 (( > ! 4 9;; 1 % 1 (( % 4 6 r '0' ( (m 0m 4 9 10 1%m 0m 4 9 120 1%m2 0m 4 9 1( 1%m ('k 4 9 12( 1%m2 ('k 4 9 (0 ( - 0m 4 9 0 # 4 0m 4/ d * 4/ 9; r ' ' 4/ @; r ' ' 4/ @; r % ) ; r % 0 ; r 84 s29ws-n_m0_i0 december 3, 2005 preliminary figure 16.14. chip/sector erase operation timings oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h december 3, 2005 s29ws-n_m0_i0 85 preliminary 5#5%# 5!5%!1#1 # ;2 < ;% < % ) # )=#7 , (-.?# =#7 , b.@ g %% 8 :* 7 ec 1 2e 1 2f ( 0 # * %% ! / " $ " figure 16.15. program operation timing using avd# oe# ce# data addresses avd# we# clk v cc 555h pd t as t avsw t avhw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs t cas 86 s29ws-n_m0_i0 december 3, 2005 preliminary 5#5%# 5!5%!1#1 # ;2 < ;% < % ) # )=#7 , (-.?# =#7 , b.@ g %% 8 :* 7 # ec ( #1! 8 % %% %% 8 - 0 * %% ! / " $ " 0 " % * " $ figure 16.16. program operation timing using clk in relationship to avd# oe# ce# data addresses we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc avd# december 3, 2005 s29ws-n_m0_i0 87 preliminary i % % / % figure 16.17. accelerated unlock bypass programming timing * 1#1 # 0 * 8 % , % # % % ! 5 figure 16.18. data# polling timings (during embedded algorithm) ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id v il or v ih t vid t vids we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data 88 s29ws-n_m0_i0 december 3, 2005 preliminary * 1#1 # 0 * 8 % , % # % % figure 16.19. toggle bit timings (during embedded algorithm) 0 % % * % 1#1 # 0 * 8 % , % # % % ) "!p / ?!b " @, !b& " "!p / :* figure 16.20. synchronous data polling timings/toggle bit timings we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc december 3, 2005 s29ws-n_m0_i0 89 preliminary !' * #1! / figure 16.21. conditions for incorrect dq2 polling during erase suspend !' / % * / # / #1! figure 16.22. correct dq2 polling during erase suspend #1 !' / % *#1! / # / figure 16.23. correct dq2 polling during erase suspend #2 !' / % * #1! / # figure 16.24. correct dq2 polling during erase suspend #3 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200n s addr ce# avd# oe# 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns 2 addr ce# avd# oe# 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns addr ce# avd# oe# 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns addr ce# avd# oe# 90 s29ws-n_m0_i0 december 3, 2005 preliminary "!p?@/ ?!b " @ "!p? @/ :* ?!b& " @ ) >> : !>> >% -& !-& 7 / : % % ( "!p 8 , ( figure 16.26. latency with boundary crossing when frequency > 66 mhz enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing !' * 0 * %%* h !' !'- figure 16.25. dq2 vs. dq6 clk address (hex) c124 c125 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(2) latency t racc t racc t racc t racc december 3, 2005 s29ws-n_m0_i0 91 preliminary "!p?@/ ?!b " @ "!p? @/ :* ?!b& " @ ) >> : !>> >% -& !-& 7 / : % % ( "!p 8 , ( figure 16.27. latency with boundary crossing into program/erase bank clk address (hex) c124 c125 c126 c127 c127 d124 d125 d126 d127 read status (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f latency rdy(2) latency t racc t racc t racc t racc 92 s29ws-n_m0_i0 december 3, 2005 preliminary '#0 ( %$ $#%1 !)! !;< ? " / !)! !;&< ? " / !)! !;&< ? ( %% + !)! !;&&< ? 7 %% - !)! !;&< ? ) %% ( % !& * ;&< figure 16.28. example of wait states insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45 december 3, 2005 s29ws-n_m0_i0 93 preliminary 3 : / % * %%* * *% ; * :< : % ; *< :0 * % / % figure 16.29. back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t ds t dh t oe t as t ah t acc t oeh t wp t ghwl t oez t write cycle t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph t write cycle t read cycle t read cycle 94 s29ws-n_m0_i0 december 3, 2005 preliminary (6;<;* / 0* % % % l ( b11 &&&& * : i d&s1 +&1&&&&&* ) 0* %% % * %>%% %% % a , 3 7 2 %% % % %% && ( * % / / % 8 > * 8 %%% # > % %% - " # . ; 6" % 0% <% + , %% %% a parameter ty p (note 1) max (note 2) unit comments =<k) 1 (( ;= d9 / ;; # < 6=k) 1 (( ^;69 @ ( 1 (( 69d=0@9=# 77<06@:# d;:0@9=# 69<06@:# (( 6d;=0@9=# =9:06@:# @=@0@9=# 6d@06@:# 0 # 7 1 (( <; <;; r (( @< @<; 0 , 0 f 1 (( 8< 8< r (( = =; d@*0f 1 (( d;; d;;; r (( 68@ 68@; ( # d 1 (( 697d0@9=# 7:=06@:# d6<=0@9=# 697d06@:# / # 9 (( 6;;70@9=# 9;d06@:# @;6d0@9=# 6;;706@:# december 3, 2005 s29ws-n_m0_i0 95 preliminary (6;<;< %&% $ % &&r 0 0 # ( &$fa parameter symbol parameter description test setup typ. max unit ( # ( 1 # o; 9d =d ! ( $j $ ( 1 $j o; 9: =: ! ( #@ ( ( 1 # o; =d 7d ! 96 s29ws-n_m0_i0 december 3, 2005 preliminary 17 appendix ) ) ! ! ) > * @9 / 0 ))) ))) 5 december 3, 2005 s29ws-n_m0_i0 97 preliminary table 17.1 memory array commands #h % (=5 # -" " " #b" > = 6 > >% > 7 6sss!; * : 4 % < 999 @ 99 xf y999 8; xf ys;; ;;;6 % % 8 = 999 @ 99 xf y999 8; xf ys;6 @@7 f cs; % f cs;! @@;; f 6; < 999 @ 99 xf y999 8; xf ys;d % < 999 @ 99 999 ; % 0 f 66 = 999 @ 99 @9 0( % 0f' % f ! 6 @8 0 f > 6@ d 999 @ 99 999 !; ( = 999 @ 99 999 :; 999 @ 99 999 6; = 999 @ 99 999 :; 999 @ 99 d; e 6d 6 f f; e > 6< 6f d; ( > 6: < 999 @ 99 999 %; s;; (> > ( > < 999 @ 99 999 (= s;; (> (! 3 69 6xf y9998: j -f 4 d 999 @ 99 999 @; 6= @sss ; % (! 6= 6sss8: > @ sss 8; sss ;; d 999 @ 99 999 :: 67 < 999 @ 99 999 ; % > 67 6 % / 67 < 999 @ 99 999 8; sss ;; 4! g "#" # "!" ! 5#5%# # #1! / ec / 5!5%!! , / # # , (-. # )=#7 , b.# =#7 3#3 :# , (-.# )=# & , b.# =# & " " !(=!& ,3e, 3 e # % % 5# ,, .% % 0 # / > % ) * 7 # g ? >% 7 @ ( , / % % 8 %* / : 0 * %% %% / * - . :%% * 8 : * + " %% 8 *? % / * @ : % !'( ? : / % @ % :6 : b 0 * %% / : # % % d ! * ( )&?, (-.@ )?, b.@ & 0 & / 0 % * %% 8 % * % %% 8 / >%% ) * %%* % % % 0 %% / * 8 : 7 " % %% / * % 8 : ( %% / / * * / % # 8 (( / (((, (-.6 b. - " 8 *%% 8 > i : 3* " %% 8 * + " 8 *%% 8 > >" %% 8 > % / %* : b " 8 %% " 98 s29ws-n_m0_i0 december 3, 2005 preliminary table 17.2. sector protection commands #h % (=d # -" " " #b" #" ' - > f ( 9 d 999 @ 99 999 <; = 6@ @ ss ; 77e;; > = 6 77 ( /7 @ ss 8; ss ;; ) ( 9 d 999 @ 99 999 =; x;*dy: @ ss ; ;; 0%x;*dy > 8 < ;;; 0%; ;;6 0%6 ;;@ 0%@ ;;d 0%d j - 7 ;; @9 ;; ;d ;; 0%; ;6 0%6;@ 0%@;d 0%d;; @8 ( /7 @ ss 8; ss ;; # *1 f ( 9 d 999 @ 99 xf y999 (; f 6; @ ss ; ;; f 6; 66 @ ss :; ;; d; f > 6 >%; ( /7 @ ss 8; ss ;; i 1 ! , f' - ( 9 d 999 @ 99 xf y999 9; f' -f @ ss ; ss ;; f' -f > 6 f >%; ( /7 @ ss 8; ss ;; 1 %lf ( 9 d 999 @ 99 xf y999 ; %lf @ ss ; ;; %lf( @ ss ; ;6 %lf > 6 >%; ( /7 @ ss 8; ss ;; 4! g "## % %* 5!?&@ e:35!?& @ t&u 5!?@5 5 $ e:35!?@ tu% j&g 5!? @ t u% jg 5!? @5 5 $ e :35!? @ t u% j&g 5!?@ tu% jg 5!?)@5 $ h 0535!?)@ t)u # # , (-.# )=#7 , b.# =#7 3#3 :# , (-.# )=# & , b.# =# & 5,!)=5,!&5 !5!)=5!& - % -7 5 5,#5 # # # #& - -7 * 5,!5 ! "!?&@"!?@"!? @!'&!' !' 2 !'&!'!' &2 !'&!' !' # / > % * ) # g ? >% 7 @ 7 , / % % 8 %* / : 0 * %% %% / * ( *%% 8 % */ % - 2 5 5 $ e: 3 5 5 $ e: 3 % % %% / 5 5 $ * . / 8 && *++ , (-. * 0 ) ) > : + >%% % / % / %* : b * 8 % d 8 & ) ;# 553 <%% % 553 / / 0 * : % ++ d, (-. / , b. && december 3, 2005 s29ws-n_m0_i0 99 preliminary 17.1 common flash memory interface ( ! (! ) * - ) ) * *) ) * v%( %* * )* -*)* ! , / * (! 3 ) ) (! 3 8: f 999 (! 67da67= ) - (! ) - * > - * ) ) (! ) ) ( / (! / > ee / !/ i g 9 ))) ))) 5 ! ) /* example: cfi entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ ! (! v%( v 6d7* v%=:;6 (! 6;; table 17.3. cfi query identification string addresses data description 6; 66 6@ ;;96 ;;9@ ;;98 3 j + ( "3>l& 6d 6< ;;;@ ;;;; $4( 69 6= ;;<; ;;;; / 67 6: ;;;; ;;;; $4( ;;o / 68 6 ;;;; ;;;; $4/ ;;o / table 17.4. system interface string addresses data description 6f ;;67 1 (( 4 ) e %7a%<. %da%;.6;; 6( ;;68 1 (( 4/) e %7a%<. %da%;.6;; 6% ;;;; 1 4 ;;o 1 6 ;;;; 1 4/ ;;o 1 6! ;;;= e)) @ r @; ;;;8 4 , ) @ r;;o @6 ;;; - @ @@ ;;;; @ ;;o @d ;;;< 4/ e)) @ @< ;;;< 4/ ) @ @9 ;;;d 4/ - @ @= ;;;; 4/ @ ;;o 100 s29ws-n_m0_i0 december 3, 2005 preliminary table 17.5. device geometry definition addresses data description @7 ;;680@9=# ;;6:06@:# % , o@ @: @8 ;;;6 ;;;; !% @ @f ;;;= ;;;; 4/ * ) o@ ;;o @( ;;;d # f -> ) @% @ @! d; ;;;d ;;;; ;;:; ;;;; f -> 6 d6 ;;!%0@9=# ;;7%06@:# f -> @ d@ dd d< ;;;; ;;;; ;;;@ d9 d= d7 d: ;;;d ;;;; ;;:; ;;;; f -> d d8 d df d( ;;;; ;;;; ;;;; ;;;; f -> < december 3, 2005 s29ws-n_m0_i0 101 preliminary table 17.6. primary vendor-specific extended query addresses data description <; <6 <@ ;;9; ;;9@ ;;<8 3 * + ( " > & ( <9 ;6;; j -f6*; ;o> + 6o#> + f9*@;6;;o;66r <= ;;;@ ;o# 6o> $ @o> g0 <7 ;;;6 ;o# so# <: ;;;; j ;;o# ;6o <8 ;;;: ej ;:o < ;;!d0@9=# ;;7f06@:# $ # - / - ;6o <( ;;;; 4 ;;o# ;6o<0 ;@o:0 ;<o6=0 <% ;;:9 (( 4 ;;o# %7*%<.1 %d*%;.6;; 1 < ;;89 (( 4/ ;;o# %7*%<.1 %d*%;.6;; 1 f% 9; ;;;6 ;;o 96 ;;;6 j -f ;;o# ;6o 9@ ;;;7 ( $ , @ 9d ;;6< 2) > ') * 4/ @ 9< ;;6< 2) > ') * 4/ @ 99 ;;;9 * 4/ @ 9= ;;;9 * 4/ @ 97 ;;6; f -$ , .so# - 9: ;;6d0@9=# ;;;f06@:# f -;> so# - 98 ;;6;0@9=# ;;;:06@:# f -6> so# - 102 s29ws-n_m0_i0 december 3, 2005 preliminary 9 ;;6;0@9=# ;;;:06@:# f -@> so# - 9f ;;6;0@9=# ;;;:06@:# f -d> so# - 9( ;;6;0@9=# ;;;:06@:# f -<> so# - 9% ;;6;0@9=# ;;;:06@:# f -9> so# - 9 ;;6;0@9=# ;;;:06@:# f -=> so# - 9! ;;6;0@9=# ;;;:06@:# f -7> so# - =; ;;6;0@9=# ;;;:06@:# f -:> so# - =6 ;;6;0@9=# ;;;:06@:# f -8> so# - =@ ;;6;0@9=# ;;;:06@:# f -6;> so# - =d ;;6;0@9=# ;;;:06@:# f -66> so# - =< ;;6;0@9=# ;;;:06@:# f -6@> so# - =9 ;;6;0@9=# ;;;:06@:# f -6d> so# - == ;;6;0@9=# ;;;:06@:# f -6<> so# - =7 ;;6d0@9=# ;;;f06@:# f -69> so# - table 17.6. primary vendor-specific extended query (continued) addresses data description december 3, 2005 s29ws-n_m0_i0 103 preliminary 18 revisions revision f (october 29, 2004) % ( p / / ) > c6 8 @;;
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